EaSyOpt: Predicting Post Place and Route Critical Paths for Early Synthesis Optimization

Walter Lau received the M.Sc. degree in Microelectronics from Universidade Federal do Rio Grande do Sul (UFRGS) in 2018, in Porto Alegre, Brazil. He is currently pursuing a Ph.D. in Computer Engineering at the University of Utah. During the summer of 2020, he is a software engineer intern with Cadence Design Systems. His research interests include digital circuit design, electronic design automation (EDA), logic synthesis, and machine learning applied to EDA.