The time zone for each day is as follows:

  1. Day 1: Monday, July 27 in Pacific Time (PT)
  2. Day 2: Wednesday, July 29 in Japan Standard Time (JST)
  3. Day 3: Thursday, July 30 in Central European Summer Time (CEST)
Day 1 Monday, July 27, 8:50am to 2:45pm Tuesday, July 28, 0:50am to 6:45am Monday, July 27 5:50pm to 11:45pm
Day 2 Tuesday, July 28, 5pm to 10:25pm Wednesday, July 29, 9am to 2:25pm Wednesday, July 29, 2am to 7:25am
Day 3 Thursday, July 30, 0am to 4:25am Thursday, July 30, 4pm to 8:25pm Thursday, July 30, 9am to 1:25pm

The zoom link to each session is only available to speakers and registered attendees.

Access to Zoom link HERE.


The proceedings are available through the following LINK.

  • Monday 27 Jul 2020
  • Wednesday 29 Jul 2020
  • Thursday 30 Jul 2020

Monday 27 Jul 2020

8:50 am - 9:00 am Opening

General/Program Chairs: Pierre-Emmanuel Gaillardon, Heinz Riener, Luca Amaru

9:00 am - 10:00 am Keynote 1: Accelerator Synthesis for Agile Hardware Specialization: A New Dawn

Moderator: Heinz Riener
Speaker: Zhiru Zhang
Session page:

10:00 am - 10:30 am Break

break 1

10:30 am - 11:45 am Session 1: To SAT solve, or not to SAT solve

Moderator: Vinicius Callegaro
Session page:

Determining the Multiplicative Complexity of Boolean Functions using SAT

Mathias Soeken

Mathias Soeken is a senior software engineer at the Quantum group at Microsoft.
Mon 10:30 am - 11:45 am

SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies

Marcel Walter

Marcel Walter received his Master’s degree in Computer Science from the University of Bremen, Germany, in 2016. He is currently in the final stage of pursuing a Ph.D. degree with the Research Group of Computer Architecture at the same university. His research interests include formal methods and algorithm design for emerging post-CMOS technologies. He is the initiator and maintainer of the “fiction” framework for design automation of Field-coupled Nanotechnologies.
Mon 10:30 am - 11:45 am

Simulation-Guided Boolean Resubstitution

Siang-Yun Lee

Siang-Yun Lee is a first-year Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli. She graduated last year from National Taiwan University, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis. Her research interests include logic synthesis and computational neuroscience.
Mon 10:30 am - 11:45 am

11:45 am - 12:15 pm Break


12:15 pm - 1:15 pm Programming Contest Session

Moderator: Gai Liu
Speakers: Alan Mishchenko, Sat Chatterjee, and Gai Liu
Session page:

1:15 pm - 1:30 pm Break

break 2

1:30 pm - 2:45 pm Special Session: The Challenges of Automating the Design Flow of Superconducting Electronic Circuits

Moderator: Tsung-Yi Ho
Session page:

Wednesday 29 Jul 2020

9:00 am - 10:00 am Keynote 2: Recent Topics and Future Perspectives on BDD/ZDD-Based Discrete Structure Manipulation

Moderator: Luca Amaru
Speaker: Shin-ichi Minato
Session page:

10:00 am - 10:30 am Break

Break 2-1

10:30 am - 11:45 am Session 2: Approximate synthesis and fault equivalence identification

Moderator: Jie-Hong Roland Jiang
Session page:

A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing

Sina Asadi

I have got my MSc from Sharif University of Technologies, and BSc from Amirkabir University of Technologies, both located in Tehran, IRAN, and both in computer engineering. Currently, I am working on stochastic computing and neural networks.
Wed 10:30 am - 11:45 am

Exploring Target Function Approximation for Stochastic Circuit Minimization

Chen Wang

Chen Wang is now a Ph.D student at University of Michigan-Shanghai Jiao Tong University Joint Institute with the major of electronic design automation. His research interests lie in the synthesis and optimization of the stochastic circuit, approximate circuit design, and circuit design of emerging technologies. He has published several papers on stochastic circuit synthesis and physical design of the carbon-nanotube field effect transistor (CNFET) circuit.
Wed 10:30 am - 11:45 am

SAT-Based Sequential Fault Equivalence Identification in Functional Safety Verification

Ai Quoc Dao

Ai Quoc Dao received the B.S. (2012) and M.S. (2015) degrees in Department of Electrical Engineering, HCMC University of Technology and Education, Ho Chi Minh City, Vietnam. She is currently working toward the Ph.D. degree in Department of Electrical Engineering National Chung Cheng University, Chiayi, Taiwan. Her research interests focus on various electronic design automation problems, specifically in logic synthesis and verification.
Wed 10:30 am - 11:45 am

11:45 am - 12:15 pm Break


12:15 pm - 1:30 pm Session 3: Optimize your functions: new heuristic and exact methods

Moderator: Alan Mishchenko
Session page:

Auto-tuning framework for BDD packages

Yukio Miyasaka

Yukio Miyasaka received the B.E. and M.E. degrees from the University of Tokyo, Japan, in 2018 and 2020 respectively. His research interests include logic synthesis, formal verification, and high-performance computing.
Wed 12:15 pm - 1:30 pm

Practical Multi-armed Bandits in Boolean Optimization

Cunxi Yu

Cunxi Yu is an Assistant Professor in the ECE Department at the University of Utah. Cunxi was a PostDoc Cornell University in 2018-2019, and a PostDoc at EPFL in 2017-2018. He received Ph.D. degree from UMass Amherst in 2017.
Wed 12:15 pm - 1:30 pm

Reduction Methods of Variables for Large-Scale Classification Functions

Tsutomu Sasao

Tsutomu Sasao received the B.E., M.E., and Ph.D. degrees in Electronics Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977, respectively. He has held faculty/research positions at Osaka University, Japan; IBM T. J. Watson Research Center, Yorktown Height, NY; the Naval Postgraduate School, Monterey, CA; Kyushu Institute of Technology, Japan; and Meiji University, Kawasaki, Japan. Currently, he is a visiting researcher of Meiji University, Japan. He is a Life Fellow of the IEEE, and has published many books on logic design.
Wed 12:15 pm - 1:30 pm

1:30 pm - 1:45 pm Break

Break 2-2

1:45 pm - 2:25 pm Session 4: Compress and secure your data: Synthesis can help

Moderator: Zhufei Chu
Session page:

Design Optimization for Faster Fp256 Elliptic Curve Cryptography

Kento Ikeda

Mr. Kento Ikeda received his BE degree from electrical engineering, the University of Tokyo in 2019, and is now pursuing his Master degree at Electrical Engineering and Information Systems, the University of Tokyo. His research interests including hardware implementation of Elliptic-curve-based cryptography. He is a member of IEEE.
Wed 1:45 pm - 2:25 pm

Lossless compression via two-level logic minimization: a case study using Chess endgame data

Dave Gomboc

Dave Gomboc holds an M.Sc. in Computing Science from the University of Alberta. He has held staff positions at the University of Alberta and the University of Southern California, where he made contributions to eXplainable Artificial Intelligence. Dave currently works full-time in industry, and pursues a Ph.D. in his spare time at the University of California, Riverside.
Wed 1:45 pm - 2:25 pm

Thursday 30 Jul 2020

9:00 am - 10:00 am Keynote 3: Logic Synthesis for optimizing the performance of SW-based Homomorphic calculations

Keynote 3: Olivier Heron, CEA List
Chair: Pierre-Emmanuel Gaillardon
Session page:

10:00 am - 10:30 am Break

Break 3-1

10:30 am - 11:45 am Session 5: XORs are fun!

Moderator: Petr Fišer
Session page:

Symbolic Uniform Sampling with XOR Circuits

Yen-Ting Lin

Yen-Ting, Lin is currently a master student working with Professor Jie-Hong Roland Jiang at National Taiwan University in Taipei, Taiwan. His research focuses on logic synthesis and electronic design automation. This is his first paper to the international workshop.
Thu 10:30 am - 11:45 am

Three-Input Gates for Logic Synthesis

Dewmini Sudara Marakkalage

Dewmini Sudara Marakkalage is a Masters’s student in Computer Science at EPFL. She is currently doing her master’s project with Synopsys working on Logic Synthesis algorithms using Majority Inverter Graphs.
Thu 10:30 am - 11:45 am

XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Shubham Rai

Shubham Rai received the B.Engg. in electrical and electronic engineering and M.Sc. in Physics from Birla Institute of Technology and Science Pilani, India, in 2011. He is currently working towards the PhD degree at Technische Universität, Dresden, Germany. His research focuses on developing design flows for emerging reconfigurable nanotechnologies and exploring how such emerging technologies can be integrated for hardware security applications.
Thu 10:30 am - 11:45 am

11:45 am - 11:55 am Updates on the EPFL logic synthesis and ECO benchmarks

11:55 am - 12:25 pm Break

Break 3-2

12:25 pm - 1:15 pm Session 6: Predict and design your critical paths

Moderator: Mathias Soeken
Session page:

EaSyOpt: Predicting Post Place and Route Critical Paths for Early Synthesis Optimization

Walter Lau

Walter Lau received the M.Sc. degree in Microelectronics from Universidade Federal do Rio Grande do Sul (UFRGS) in 2018, in Porto Alegre, Brazil. He is currently pursuing a Ph.D. in Computer Engineering at the University of Utah. During the summer of 2020, he is a software engineer intern with Cadence Design Systems. His research interests include digital circuit design, electronic design automation (EDA), logic synthesis, and machine learning applied to EDA.
Thu 12:25 pm - 1:15 pm

Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling

Yutaka Masuda

Yutaka Masuda received the B.E., M.E., and Ph.D. degrees in Information Systems Engineering from the Osaka University,Osaka, Japan, in 2014, 2016, and 2019, respectively. He is currently an Assistant Professor in Center for Embedded Computing Systems, Graduate School of Informatics, Nagoya University. His research interests include low-power circuit design and testing. He is a member of IEEE, IEICE, and IPSJ.
Thu 12:25 pm - 1:15 pm

1:15 pm - 1:25 pm Closing

Chair: Pierre-Emmanuel Gaillardon