Three-Input Gates for Logic Synthesis

Three-Input Gates for Logic Synthesis

Dewmini Sudara Marakkalage

Dewmini Sudara Marakkalage is a Masters’s student in Computer Science at EPFL. She is currently doing her master’s project with Synopsys working on Logic Synthesis algorithms using Majority Inverter Graphs.
Fri 1:40 pm - 12:00 am