Simulation-Guided Boolean Resubstitution
Siang-Yun Lee is a first-year Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli. She graduated last year from National Taiwan University, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis. Her research interests include logic synthesis and computational neuroscience.
Fri 3:31 pm - 12:00 am