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Session: Session 2: Approximate synthesis and fault equivalence identification

Moderator: Jie-Hong Roland Jiang
Session page: https://iwls20.cade.utah.edu/session-2-internal/

SAT-Based Sequential Fault Equivalence Identification in Functional Safety Verification

A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing

Exploring Target Function Approximation for Stochastic Circuit Minimization

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